CO C4 Hardware and Software

RECALL

The organization of a computer:

Introduction & Logic Design Conventions

recall

• CPU performance factors:

  1. Instruction count determined by ISA and compiler;
  2. CPI and Cycle time determined by CPU hardware.

  $$CPU\quad Time = IC \times CPI \times T_c$$

• Simple subset shows most aspects.

  1. Memory reference
  2. Arithmetic / Logical
  3. Control transfer

Instruction execution

1. IF: Fetch the instruction from the memory.

2. ID: Decode and read the registers at the same time.

   Read the data at rs1,rs2 of R-type instruction under all circumstances.

   Drop the data read if the instruction doesn’t require reading data.

3. EX: Use ALU to calculate

   • Arithmetic result
   • Memory address for load/store
   • Branch comparison to judge

4. MEM,WB: Access data memory for load /store.

5. UPC: Update PC with PC + 4 or target address( branch or jump).

A simple implementation

单周期CPU的特点：由于部件访问以来时钟信号，无法在一个时钟周期内访问两次相同部件。故导致部件冗余。

• Instruction memory, Data memory
• Adder, ALU
• Program Counter
• Immediate generator
• Multiplexer
• Register Files

ALU

• Input: A(32),B(32),Operation(4)
• Output: Result(32),Overflow(1),Zero(1)

slt, Set on less than means

If A < B then
	Result = 1;
else
	Result = 0;

Register

• Input: In(32),Write(1)
• Output: Out(32)

State element controlled by Write signal:

• 0: remains constant;
• 1: store the input into register when positive edge of clk comes.

Register Files

Register Files consists of 32 32/64-bit Registers.

• Input: ReadR1(5),ReadR2(5),WriteR(5),WriteData(32),RegWrite(1)
• Output: ReadD1(32),ReadD2(32)

module regs(input clk, rst, RegWrite,
            input [4:0] Rs1_addr, Rs2_addr, Wt_addr,
            input [63:0] Wt_data, 
            output [63:0] Rs1_data, Rs2_data); 
reg [63:0] register [1:31]; // r1 - r31
integer i; 
assign rdata_A = (Rs1_addr== 0) ? 0 : register[Rs1_addr];
assign rdata_B = (Rs2_addr== 0) ? 0 : register[Rs2_addr];
always @(posedge clk or posedge rst) begin 
    if (rst==1)
	for (i=1; i<32; i=i+1) register[i] <= 0;
	else if ((Wt_addr != 0) && (RegWrite == 1)) register[Wt_addr] <= Wt_data;
end
endmodule

Memory

Instruction memory, read only

• Input: Address(32)
• Output: Instruction(32)

Data memory

• Input: Address(32),WriteData(32),MemWrite/MemRead(1)
• Output: ReadData(32)

Immediate generation unit

• Input: Instruction(32)
• Output: Immediate(32)

L_imm = {{52{inst[31]}},inst[31:20]};
S_imm = {{52{inst[31]}},inst[31:25],inst[11:7]};
SB_imm = {{51{inst[31]}},inst[31],inst[7],inst[30:25],inst[11:8],1'b0};
UJ_imm = {{43{inst[31]}},inst[31],inst[19:12],inst[20],inst[30:21],1'b0};

CPU Overview

A simple overview and MUX

Overview with Control

Logic Design Conventions

Information encoded in binary  Low voltage = 0, High voltage = 1  One wire per bit  Multi-bit data encoded on multi-wire buses
Combinational element  Operate on data  Output is a function of input
State (sequential) elements
 Store information

Clocking Methodology: Edge triggered

• read contents of some state elements;
• send values through some combinational logic
• write results to one or more state elements

Building a datapath

Datapath: Elements that process data and addresses in the CPU such as Registers, ALUs, mux’s, memories, …

Instruction fetching

Take instructions from the instruction memory and Modify PC to point the next instruction (But PC not updated until the end of the clock cycle!).

Path Built using Multiplexer

R-type instruction Datapath

1. Read 2 register operands.
2. Perform arithmetic or logical operation.
3. Write register result.

(/img/posts/CO/4_7.png)

I-type instruction Datapath

• For ALU
  1.
• For load

S-type (store) instruction Datapath

SB-type (branch) instruction Datapath

UJ-type instruction Datapath

A Simple Implementation Scheme

Pipelining