Tek's Notes

HW4 Processor

4.1

4.1.1

Inst	ALUsrc	MemtoReg	RegW	MemR	MemW	Branch	Jump	ALUop1	ALUop2	alu op
And	0	0	1	0	0	0	0	1	0	and

4.1.2

ALUsrc mux, ALU, MemtoReg mux.

4.1.3

All blocks produces some output. The output for datamemory and ImmGen is not used.

4.4

4.4.1

all kinds of load instructions and jal instructions are broken.

4.4.2

all instructions uses immediates to calculate like I-type(immediate), storeand load(address calculating) are broken.

4.6

4.6.1

There’s no need to add blocks.

4.6.2

Inst	ALUsrc	MemtoReg	RegW	MemR	MemW	Branch	Jump	ALUop	alu op
Addi	1	00	1	0	0	0	0	10	add

4.7

4.7.1

$$L_{R-type} = 30({\small PCa}) + 250({\small Imem}) + 150({\small} Regs) + 25({\small ALUsrc}) + 200 + 25({\small DataWite}) + 20(Setup) = 700ps$$

4.7.2

$$L_{ld} = 30 + 250 + 150 + 200 + 250({\small Dmem}) + 25({\small DataWite}) + 20(Setup) = 925ps$$

4.7.3

$$L_{sd} = 30 + 250 + 150({\small Reg\ covers}) + 200 = 630ps$$

4.7.4

$$L_{beq} = 30 + 250 + 150 + 25({\small ALUsrc}) + 200 + 5({\small single\ and}) + 25 ({\small branch}) + 20(Setup) = 705ps$$

4.7.5

$$L_{I-type} = 30 + 250 + 150 + 200 + 25({\small DataWite}) + 20(Setup) = 675ps$$

4.7.6

The minimum clock period for this CPU is the maximum of the latency, i.e. 925ps.

4.8

For a CPU where the clock cycle time was different for each instruction:

$$CPI_{avg} = 0.52\times700 + 0.25\times925+0.11\times630+0.12\times705= 749.15ps$$

For a CPU shown in 4.21:

$$CPI = 925ps$$

The speedup is

$$S = \frac{CPI_{avg}}{CPI} = 1.235$$

4.13

4.13.1,2,3

We need add a mux to select address to witre to memory; a mux to select data to write to memory.

Also the matching control signal should be generated by CONTROL to select.

4.13.4

Inst	ALUsrc	MemtoReg	RegW	MemR	MemW	Branch	Jump	ALUop	ss
ss	1	X	0	0	1	0	0	10(add)	1

4.13.5